The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures that include stacked field-effect transistors and methods for forming a structure that includes stacked field-effect transistors.
Static random access memory (SRAM) may be used, for example, to temporarily store data in a computer system. When continuously powered, the memory state of an SRAM persists without the need for data refresh operations. An SRAM device includes an array of bitcells in which each bitcell retains a single bit of data during operation. Each SRAM bitcell may include a pair of cross-coupled inverters and a pair of access transistors connecting the inverters to complementary bit lines. The two access transistors are controlled by word lines, which are used to select the SRAM bitcell for read or write operations.
Traditional complementary metal-oxide-semiconductor (CMOS) structures for a field-effect transistor include a source, a drain, a channel situated between the source and drain, and a gate electrode configured to respond to a gate voltage by selectively connecting the source and drain to each other through the channel. Field-effect transistor structures can be broadly categorized based upon the orientation of the channel relative to a surface of a semiconductor substrate associated with their formation. Planar field-effect transistors and fin-type field-effect transistors constitute a category of transistor structures in which the flow of gated current in the channel is oriented in a horizontal direction parallel to the substrate surface.
Improved structures that include stacked field-effect transistors and methods for forming a structure that includes stacked field-effect transistors are needed.